Complete Formal Hardware Verification of Interfaces for a FlexRay-Like Bus

Müller, Christian A. and Paul, Wolfgang J.
(2011) Complete Formal Hardware Verification of Interfaces for a FlexRay-Like Bus.
In: Computer Aided Verification - 23rd International Conference, CAV 2011, Snowbird, UT, USA, July 14-20, 2011. Proceedings.
Conference: CAV Computer Aided Verification

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Official URL: https://doi.org/10.1007/978-3-642-22110-1_51

Abstract

We report the first complete formal verification of a time-triggered bus interface at the gate and register level. We discuss hardware models for multiple clock domains and we review known results and proof techniques about the essential components of such bus interfaces: among others serial interfaces, clock synchronization and bus control. Combining such results into a single proof leads to an amazingly subtle theory about the realization of direct connections between units (as assumed in existing correctness proofs for components of interfaces) by properly controlled time-triggered buses. It also requires an induction arguing simultaneously about bit transmission across clock domains, clock synchronization and bus control.

Item Type: Conference or Workshop Item (A Paper) (Paper)
Conference: CAV Computer Aided Verification
Depositing User: Sebastian Weisgerber
Date Deposited: 23 Feb 2018 12:31
Last Modified: 23 Feb 2018 13:15
URI: https://publications.cispa.saarland/id/eprint/2464

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