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Semantic Scholar21. ASP-DAC 2016: Macao, Macao
21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016, Macao, Macao, January 25-28, 2016. IEEE 2016, ISBN 978-1-4673-9569-4- Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa:
An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection. 1-2 - Chak-Fong Cheang, Ka-Fai Un, Pui-In Mak, Rui Paulo Martins:
Time-domain I/Q-LOFT compensator using a simple envelope detector for a sub-GHz IEEE 802.11af WLAN transmitter. 3-4 - Aravind Tharayil Narayanan, Makihiko Katsuragi, Kengo Nakata, Yuki Terashima, Kenichi Okada, Akira Matsuzawa:
A noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique. 5-6 - Bo Wang, Man Kay Law, Saqib Mohamad, Amine Bermak:
A 2.2µW 15b incremental delta-sigma ADC with output-driven input segmentation. 7-8 - Minkyu Song, Joseph Sankman, Jayeol Lee, Dongsheng Brian Ma:
A 200-MHz 4-phase fully integrated voltage regulator with local ground sensing dual loop ZDS hysteretic control using 6.5nH package bondwire inductors on 65nm bulk CMOS. 9-10 - Yuan Gao, Lisong Li, Philip K. T. Mok:
An AC powered converter-free LED driver with low flicker. 11-12 - An-Tia Xiao, Yung-Siang Miao, Ching-Hwa Cheng, Jiun-In Guo:
A variable-voltage low-power technique for digital circuit system. 13-14 - Mingzhong Li, Chio-In Ieong, Man-Kay Law, Pui-In Mak, Mang I Vai, Sio-Hang Pun, Rui Paulo Martins:
Sub-threshold VLSI logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniques. 15-16 - Liang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen, Jai-Ming Lin:
A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. 17-18 - Qing Lu, Chiu-Wing Sham, Francis C. M. Lau:
Rapid prototyping of multi-mode QC-LDPC decoder for 802.11n/ac standard. 19-20 - Chio-In Ieong, Pui-In Mak, Mang I Vai, Rui Paulo Martins:
Sub-µW QRS detection processor using quadratic spline wavelet transform and maxima modulus pair recognition for power-efficient wireless arrhythmia monitoring. 21-22 - Kiichi Niitsu, Atsuki Kobayashi, Yudai Ogawa, Matsuhiko Nishizawa, Kazuo Nakazato:
Design of an energy-autonomous, disposable, supply-sensing biosensor using bio fuel cell and 0.23-V 0.25-µm zero-Vth all-digital CMOS supply-controlled ring oscillator with inductive transmitter. 23-24 - Shuo Wang, Yun Liang, Chao Zhang, Xiaolong Xie, Guangyu Sun, Yongpan Liu, Yu Wang, Xiuhong Li:
Performance-centric register file design for GPUs using racetrack memory. 25-30 - Lei Jiang, Wujie Wen, Danghui Wang, Lide Duan:
Improving read performance of STT-MRAM based main memories through Smash Read and Flexible Read. 31-36 - Mingyu Wang, Zhaolin Li:
STLAC: A spatial and temporal locality-aware cache and network-on-chip codesign for tiled many-core systems. 37-42 - Roberto Vargas, Sara Royuela, Maria A. Serrano, Xavier Martorell, Eduardo Quiñones:
A lightweight OpenMP4 run-time for embedded systems. 43-49 - Tao Liu, Hui Guo, Sri Parameswaran, Xiaobo Sharon Hu:
Improving tag generation for memory data authentication in embedded processor systems. 50-55 - Andrew Hennessy, Yu Zheng, Swarup Bhunia:
JTAG-based robust PCB authentication for protection against counterfeiting attacks. 56-61 - Dimitar Nikolov, Erik Larsson:
Maximizing level of confidence for non-equidistant Checkpointing. 62-68 - Chen Liu, Patrick Cronin, Chengmo Yang:
A mutual auditing framework to protect IoT against hardware Trojans. 69-74 - Jian Kuang, Junjie Ye, Evangeline F. Y. Young:
Simultaneous template optimization and mask assignment for DSA with multiple patterning. 75-82 - Seongbo Shim, Youngsoo Shin:
Mask optimization for directed self-assembly lithography: Inverse DSA and inverse lithography. 83-88 - Zhi-Wen Lin, Yao-Wen Chang:
Cut redistribution with directed self-assembly templates for advanced 1-D gridded layouts. 89-94 - Zigang Xiao, Chun-Xun Lin, Martin D. F. Wong, Hongbo Zhang:
Contact layer decomposition to enable DSA with multi-patterning technique for standard cell based layout. 95-102 - Zhaoxin Liang, Meghna G. Mankalale, Brandon Del Bel, Sachin S. Sapatnekar:
Logic and memory design using spin-based circuits. 103-108 - Ping Chi, Shuangchen Li, Yuanqing Cheng, Yu Lu, Seung H. Kang, Yuan Xie:
Architecture design with STT-RAM: Opportunities and challenges. 109-114 - Abhronil Sengupta, Karthik Yogendra, Deliang Fan, Kaushik Roy:
Prospects of efficient neural computing with arrays of magneto-metallic neurons and synapses. 115-120 - Ryan Berryhill, Andreas G. Veneris:
A complete approach to unreachable state diagnosability via property directed reachability. 127-132 - Payman Behnam, Bijan Alizadeh, Sajjad Taheri, Masahiro Fujita:
Formally analyzing fault tolerance in datapath designs using equivalence checking. 133-138 - Yi Diao, Xing Wei, Tak-Kei Lam, Yu-Liang Wu:
Coupling reverse engineering and SAT to tackle NP-complete arithmetic circuitry verification in ∼O(# of gates). 139-146 - Yizi Gu, Yongpan Liu, Yiqun Wang, Hehe Li, Huazhong Yang:
NVPsim: A simulator for architecture explorations of nonvolatile processors. 147-152 - Sebastian Ottlik, Jan Micha Borrmann, Sadik Asbach, Alexander Viehl, Wolfgang Rosenstiel, Oliver Bringmann:
Trace-based context-sensitive timing simulation considering execution path variations. 159-165 - Bin Lin, Zhenkun Yang, Kai Cong, Fei Xie:
Generating high coverage tests for SystemC designs using symbolic execution. 166-171 - Chien-Hsiung Chiou, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang:
Circular-contour-based obstacle-aware macro placement. 172-177 - Wei-Ting Jonas Chan, Kun Young Chung, Andrew B. Kahng, Nancy D. MacDonald, Siddhartha Nath:
Learning-based prediction of embedded memory timing failures during initial floorplan design. 178-185 - Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan:
Stitch aware detailed placement for multiple e-beam lithography. 186-191 - Seong-I Lei, Wai-Kei Mak, Chris Chu:
Minimum implant area-aware placement and threshold voltage refinement. 192-197 - Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni:
High-level synthesis of accelerators in embedded scalable platforms. 204-211 - Zelei Sun, Keith A. Campbell, Wei Zuo, Kyle Rupnow, Swathi T. Gurumani, Frederic Doucet, Deming Chen:
Designing high-quality hardware on a development effort budget: A study of the current state of high-level synthesis. 218-225 - Deokjin Joo, Taewhan Kim:
Clock buffer polarity assignment utilizing useful clock skews for power noise reduction. 226-231 - Inhak Han, Daijoon Hyun, Youngsoo Shin:
Buffer insertion to remove hold violations at multiple process corners. 232-237 - Louis Y.-Z. Lin, Charles H.-P. Wen:
Speed binning with high-quality structural patterns from functional timing analysis (FTA). 238-243 - Xin Huang, Valeriy Sukharev, Taeyoung Kim, Hai-Bao Chen, Sheldon X.-D. Tan:
Electromigration recovery modeling and analysis under time-dependent current and temperature stressing. 244-249 - Yu-Guang Chen, Wan-Yu Wen, Yun-Ting Wang, You-Luen Lee, Shih-Chieh Chang:
A novel low-cost dynamic logic reconfigurable structure strategy for low power optimization. 250-255 - Kyounghoon Kim, Jongeun Lee, Kiyoung Choi:
An energy-efficient random number generator for stochastic circuits. 256-261 - Shang-Yi Li, Pei-Yuan Chou, Jinn-Shyan Wang:
Design of an all-digital temperature sensor in 28 nm CMOS using temperature-sensitive delay cells and adaptive-1P calibration for error reduction. 262-267 - Hyoungseok Moon, Taewhan Kim:
Design and allocation of loosely coupled multi-bit flip-flops for power reduction in post-placement optimization. 268-273 - Chi-Ruo Wu, Wei Wen, Tsung-Yi Ho, Yiran Chen:
Thermal optimization for memristor-based hybrid neuromorphic computing systems. 274-279 - Leibin Ni, Yuhao Wang, Hao Yu, Wei Yang, Chuliang Weng, Junfeng Zhao:
An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar. 280-285 - Tao Luo, Wei Zhang, Bingsheng He, Douglas L. Maskell:
A racetrack memory based in-memory booth multiplier for cryptography application. 286-291 - Robert Wille, Oliver Keszocze, Marcel Walter, Patrick Rohrs, Anupam Chattopadhyay, Rolf Drechsler:
Look-ahead schemes for nearest neighbor optimization of 1D and 2D quantum circuits. 292-297 - Hrishikesh Jayakumar, Arnab Raha, Younghyun Kim, Soubhagya Sutar, Woo Suk Lee, Vijay Raghunathan:
Energy-efficient system design for IoT devices. 298-301 - Khondker Z. Ahmed, Monodeep Kar, Saibal Mukhopadhyay:
(Invited paper) energy delivery for self-powered IoT devices. 302-307 - Swagath Venkataramani, Kaushik Roy, Anand Raghunathan:
Efficient embedded learning for IoT devices. 308-311 - Karthik Yogendra, Deliang Fan, Yong Shim, Minsuk Koo, Kaushik Roy:
Computing with coupled Spin Torque Nano Oscillators. 312-317 - Juan Yi, Qian Zhang, Ye Tian, Ting Wang, Weichen Liu, Edwin Hsing-Mean Sha, Qiang Xu:
ApproxMap: On task allocation and scheduling for resilient applications. 318-323 - Dustin Peterson, Oliver Bringmann:
SMoSi: A framework for the derivation of sleep mode traces from RTL simulations. 330-335 - Yidi Liu, Benjamin Carrión Schäfer:
Optimization of behavioral IPs in multi-processor system-on-chips. 336-341 - Xian Zhang, Guangyu Sun, Yaojun Zhang, Yiran Chen, Hai Li, Wujie Wen, Jia Di:
A novel PUF based on cell error rate distribution of STT-RAM. 342-347 - Nitin Rathi, Swaroop Ghosh, Anirudh Iyengar, Helia Naeimi:
Data privacy in non-volatile cache: Challenges, attack models and solutions. 348-353 - Hongbin Zhang, Chao Zhang, Xian Zhang, Guangyu Sun, Jiwu Shu:
Pin Tumbler Lock: A shift based encryption mechanism for racetrack memory. 354-359 - Yuan Xue, Patrick Cronin, Chengmo Yang, Jingtong Hu:
Routing path reuse maximization for efficient NV-FPGA reconfiguration. 360-365 - Rickard Ewetz, Cheng-Kok Koh:
MCMM clock tree optimization based on slack redistribution using a reduced slack graph. 366-371 - Daohang Shi, Edward Tashjian, Azadeh Davoodi:
Dynamic planning of local congestion from varying-size vias for global routing layer assignment. 372-377 - Man-Pan Wong, Wen-Hao Liu, Ting-Chi Wang:
Negotiation-based track assignment considering local nets. 378-383 - Fengxian Jiao, Sheqin Dong:
Ordered Escape routing for grid pin array based on Min-cost Multi-commodity Flow. 384-389 - Matthias Jung, Deepak M. Mathew, Christian Weis, Norbert Wehn:
Efficient reliability management in SoCs - an approximate DRAM perspective. 390-394 - Santanu Sarma, Tiago Mück, Majid Shoushtari, Abbas BanaiyanMofrad, Nikil Dutt:
Cross-layer virtual/physical sensing and actuation for resilient heterogeneous many-core SoCs. 395-402 - Islam A. K. M. Mahfuzul, Hidetoshi Onodera:
On-chip monitoring and compensation scheme with fine-grain body biasing for robust and energy-efficient operations. 403-409 - Petra R. Maier, Veit B. Kleeberger:
Embedded software reliability testing by unit-level fault injection. 410-416 - Wandi Liu, Hai Wang, Hengyang Zhao, Shujuan Wang, Hai-Bao Chen, Yuzhuo Fu, Jian Ma, Xin Li, Sheldon X.-D. Tan:
Thermal modeling for energy-efficient smart building with advanced overfitting mitigation technique. 417-422 - Mohammad Abdullah Al Faruque, Korosh Vatanparvar:
Modeling, analysis, and optimization of Electric Vehicle HVAC systems. 423-428 - Sebastian Steinhorst, Zili Shao, Samarjit Chakraborty, Matthias Kauer, Shuai Li, Martin Lukasiewycz, Swaminathan Narayanaswamy, Muhammad Usman Rafique, Qixin Wang:
Distributed reconfigurable Battery System Management Architectures. 429-434 - Donkyu Baek, Joonki Hong, Naehyuck Chang:
Minimum-energy driving speed profiles for low-speed electric vehicles. 435 - Shih-Chun Chou, Yuan-Hao Chang, Yuan-Hung Kuan, Po-Chun Huang, Che-Wei Tsao:
Multi-version checkpointing for flash file systems. 436-443 - Wei-Lin Wang, Yuan-Hao Chang, Po-Chun Huang, Chia-Heng Tu, Hsin-Wen Wei, Wei-Kuan Shih:
Relay-based key management to support secure deletion for resource-constrained flash-memory storage devices. 444-449 - Huizhang Luo, Jingtong Hu, Liang Shi, Chun Jason Xue, Qingfeng Zhuge:
Peak-to-average pumping efficiency improvement for charge pump in Phase Change Memories. 450-455 - Xinhan Lin, Shouyi Yin, Leibo Liu, Shaojun Wei:
Exploiting parallelism of imperfect nested loops with sibling inner loops on coarse-grained reconfigurable architectures. 456-461 - Kent W. Nixon, Xiang Chen, Zhi-Hong Mao, Yiran Chen:
SlowMo - enhancing mobile gesture-based authentication schemes via sampling rate optimization. 462-467 - Mathias Soeken, Daniel Große, Arun Chandrasekharan, Rolf Drechsler:
BDD minimization for approximate computing. 474-479 - Yu-Min Chou, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang:
MajorSat: A SAT solver to majority logic. 480-485 - Yung-Chih Chen, Runyi Wang, Yan-Ping Chang:
Fast synthesis of threshold logic networks with optimization. 486-491 - M. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan:
Polysynchronous stochastic circuits. 492-498 - Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Majority-based synthesis for nanotechnologies. 499-502 - Jason Cong, Hui Huang, Mohammad Ali Ghodrat:
A scalable communication-aware compilation flow for programmable accelerators. 503-510 - Anastasis Keliris, Charalambos Konstantinou, Nektarios Georgios Tsoutsos, Raghad Baiad, Michail Maniatakos:
Enabling multi-layer cyber-security assessment of Industrial Control Systems through Hardware-In-The-Loop testbeds. 511-518 - Jacob Wurm, Khoa Hoang, Orlando Arias, Ahmad-Reza Sadeghi, Yier Jin:
Security analysis on consumer and industrial IoT devices. 519-524 - Nikolay Matyunin, Jakub Szefer, Sebastian Biedermann, Stefan Katzenbeisser:
Covert channels using mobile device's magnetic field sensors. 525-532 - Siarhei S. Zalivaka, Alexander V. Puchkov, Vladimir P. Klybik, Alexander A. Ivaniuk, Chip-Hong Chang:
Multi-valued Arbiters for quality enhancement of PUF responses on FPGA implementation. 533-538 - Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan:
Every test makes a difference: Compressing analog tests to decrease production costs. 539-544 - Fa Wang, Shihui Yin, Minhee Jun, Xin Li, Tamal Mukherjee, Rohit Negi, Larry T. Pileggi:
Re-thinking polynomial optimization: Efficient programming of reconfigurable radio frequency (RF) systems by convexification. 545-550 - Chenjie Yang, Fan Yang, Xuan Zeng, Dian Zhou:
An efficient trajectory-based algorithm for model order reduction of nonlinear systems via localized projection and global interpolation. 551-556 - Jian Deng, Haotian Liu, Kim Batselier, Yu-Kwong Kwok, Ngai Wong:
STORM: A nonlinear model order reduction method via symmetric tensor decomposition. 557-562 - Kent W. Nixon, Xiang Chen, Yiran Chen:
Footfall - GPS polling scheduler for power saving on wearable devices. 563-568 - Zhe Yuan, Yongpan Liu, Hehe Li, Huazhong Yang:
CP-FPGA: Computation data-aware software/hardware co-design for nonvolatile FPGAs based on checkpointing techniques. 569-574 - Mohammad Motamedi, Philipp Gysel, Venkatesh Akella, Soheil Ghiasi:
Design space exploration of FPGA-based Deep Convolutional Neural Networks. 575-580 - Jingyang Zhu, Zhiliang Qian, Chi-Ying Tsui:
LRADNN: High-throughput and energy-efficient Deep Neural Network accelerator using Low Rank Approximation. 581-586 - Qin Wang, Yizhong Ru, Hailong Yao, Tsung-Yi Ho, Yici Cai:
Sequence-pair-based placement and routing for flow-based microfluidic biochips. 587-592 - Jain-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho:
Congestion- and timing-driven droplet routing for pin-constrained paper-based microfluidic biochips. 593-598 - Yung-Chun Lei, Chen-Shing Hsu, Juinn-Dar Huang, Jing-Yang Jou:
Chain-based pin count minimization for general-purpose digital microfluidic biochips. 599-604 - Yi-Siang Su, Tsung-Yi Ho, Der-Tsai Lee:
A routability-driven flow routing algorithm for programmable microfluidic devices. 605-610 - Fedor G. Pikus, Andres J. Torres:
Advanced multi-patterning and hybrid lithography techniques. 611-616 - Mark Po-Hung Lin, Yao-Wen Chang, Chih-Ming Hung:
Recent research development and new challenges in analog layout synthesis. 617-622 - Xing Wei, Yi Diao, Yu-Liang Wu:
To Detect, Locate, and Mask Hardware Trojans in digital circuits by reverse engineering and functional ECO. 623-630 - Zana Ghaderi, Eli Bozorgzadeh:
Aging-aware high-level physical planning for reconfigurable systems. 631-636 - Xin He, Guihai Yan, Yinhe Han, Xiaowei Li:
ACR: Enabling computation reuse for approximate computing. 643-648 - Xinfei Guo, Mircea R. Stan:
Work hard, sleep well - Avoid irreversible IC wearout with proactive rejuvenation. 649-654 - Travis Meade, Shaojie Zhang, Yier Jin:
Netlist reverse engineering for high-level functionality reconstruction. 655-660 - Hoda Pahlevanzadeh, Jaya Dofe, Qiaoyan Yu:
Assessing CPA resistance of AES with different fault tolerance mechanisms. 661-666 - Ke Jiang, Petru Eles, Zebo Peng, Sudipta Chattopadhyay, Lejla Batina:
SPARTA: A scheduling policy for thwarting differential power analysis attacks. 667-672 - Tetsuaki Matsunawa, Bei Yu, David Z. Pan:
Laplacian eigenmaps and bayesian clustering based layout pattern sampling and its applications to hotspot detection and OPC. 679-684 - Junlong Zhou, Xiaobo Sharon Hu, Yue Ma, Tongquan Wei:
Balancing lifetime and soft-error reliability to improve system availability. 685-690 - Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region. 691-696 - Samyoung Bang, Kwangsoo Han, Andrew B. Kahng, Mulong Luo:
Delay uncertainty and signal criticality driven routing channel optimization for advanced DRAM products. 697-704 - Ulf Schlichtmann, Masanori Hashimoto, Iris Hui-Ru Jiang, Bing Li:
Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits. 705-711 - Adam Kostrzewa, Selma Saidi, Leonardo Ecco, Rolf Ernst:
Dynamic admission control for real-time networks-on-chips. 719-724 - Lei Yang, Weichen Liu, Weiwen Jiang, Mengquan Li, Juan Yi, Edwin Hsing-Mean Sha:
FoToNoC: A hierarchical management strategy based on folded lorus-like Network-on-Chip for dark silicon many-core systems. 725-730 - Li-Chung Hsu, Junichiro Kadomoto, So Hasegawa, Atsutake Kosuge, Yasuhiro Take, Tadahiro Kuroda:
Analytical thruchip inductive coupling channel design optimization. 731-736 - Sandeep Chandran, Preeti Ranjan Panda, Deepak Chauhan, Sharad Kumar, Smruti R. Sarangi:
Extending trace history through tapered summaries in post-silicon validation. 737-742 - Bingjun Xiao, Jinjun Xiong, Yiyu Shi:
Novel applications of deep learning hidden features for adaptive testing. 743-748 - Dominik Erb, Karsten Scheibler, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker:
Mixed 01X-RSL-Encoding for fast and accurate ATPG with unknowns. 749-754 - Cheng-Hung Wu, Saint James Lee, Kuen-Jong Lee:
Test and diagnosis pattern generation for dynamic bridging faults and transition delay faults. 755-760 - Ying-Yu Chen, Morteza Gholipour, Deming Chen:
Flexible transition metal dichalcogenide field-effect transistors: A circuit-level simulation study of delay and power under bending, process variation, and scaling. 761-768 - Rajendra Bishnoi, Fabian Oboril, Mehdi Baradaran Tahoori:
Non-Volatile Non-Shadow flip-flop using Spin Orbit Torque for efficient normally-off computing. 769-774 - Tiansong Cui, Shuang Chen, Yanzhi Wang, Qi Zhu, Shahin Nazarian, Massoud Pedram:
Optimal co-scheduling of HVAC control and battery management for energy-efficient buildings considering state-of-health degradation. 775-780 - Joonki Hong, Sangjun Park, Naehyuck Chang:
Accurate remaining range estimation for Electric vehicles. 781-786
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last updated on 2017-07-26 22:04 CEST by the dblp team